The present invention relates to an electrical package.
In design for testability for a semiconductor integrated circuit including a large scale logic circuit, conventionally, a scan test technique and a BIST (Built In Self Test) technique have been used. In recent years, compressed deterministic pattern test technique has often been used.
The compressed deterministic pattern test is a technique for loading compressed deterministic patterns pre-computed by automatic test pattern generation (ATPG) tool via external scan input terminals of a semiconductor integrated circuit having a number of scan chains more than the number of the external inputs, decompressing the compressed test data through an decompressor located in the semiconductor integrated circuit and distributing the decompressed test data into the respective internal scan chains, executing the scan test through the respective scan chains, and then compressing a result of the execution by a compactor located in the semiconductor integrated circuit and unload the result of the compression to a number of scan output terminals less than the number of the internal scan chains. The result of the compression which is thus output is compared with an expected value in pattern memory in an LSI tester and it is decided whether logic in the semiconductor integrated circuit is defect-free or not (for example, see Januz Rajki et al, “Embedded Deterministic Test for Low-Cost Manufacturing Test”, Proceeding International Test Conference 2002 (ITC'02), 2002, p. 301-310 (U.S.A.)).
In recent years, moreover, an electrical system package which contains a plurality of semiconductor integrated circuits of different types, for example, a logic integrated circuit or a memory integrated circuit has often been used to enhance a mounting efficiency of an electronic apparatus. The semiconductor integrated circuits contained in the package are tested preceding the assembly and any of them which are decided to be a defect-free product is assembled in the package. However, a defect is also incorporated during the package assembly. Also after the package assembly, therefore, it is necessary to test the individual semiconductor integrated circuits.
At that time, it is possible to carry out a test through the compressed deterministic pattern test technique for a compressed deterministic pattern test compatible semiconductor integrated circuit. In the case in which a plurality of compressed deterministic pattern test compatible semiconductor integrated circuits is stored in the package, however, there is a need to modify access mechanism to the scan input/output terminals of the respective semiconductor integrated circuits from an outside.
For example, in some cases in which the scan input/output terminals of the compressed deterministic pattern test compatible semiconductor integrated circuits are simply pulled out as they are, a total number thereof exceeds the number of scan data inputting/outputting terminals of the LSI tester so that the test cannot be carried out at a time. On the other hand, in the case in which a terminal to be connected to the outside is shared with the semiconductor integrated circuits, a switching circuit is required for this purpose and there is a need to consider a place in the package where the switching circuit is to be provided.
In the case in which the compressed deterministic pattern test compatible semiconductor integrated circuit and a compressed deterministic pattern test non-compatible semiconductor integrated circuit are both reside in a package, moreover, the compressed deterministic pattern test non-compatible semiconductor integrated circuit is tested through a conventional scan test. Consequently, there is a possibility that a test time might be prolonged for only the semiconductor integrated circuit.